Since the manufacturing yields for integrated circuits are below 100%, the electrical test of integrated circuits 2 that are still present on a silicon wafer 1 makes it possible to identify and reject integrated circuits that are defective or that lack the expected characteristics, before the wafer is sliced and before the individualized integrated circuits are mounted in a package or on an interconnection medium. Since mounting and assembly costs can represent up to 50% of the cost price of the finished product, this operation is essential for reducing production costs, especially in the context of mass production.
By way of an example, FIG. 1 shows a silicon wafer 1 on which a large number of integrated circuits 2 having the same structure have been made by photolithography. The magnified view of FIG. 2 shows an integrated circuit 2 with an active zone 3 and connection pads 4 electrically connected to the active zone 3. A greater magnification of the active zone 3 would reveal hundreds or even thousands of integrated circuits together constituting various electronic functions that have to be tested.
FIG. 3 gives a very schematic view of a test system comprising a test station 11 connected to a probe 12 by means of a harness of electrical cables 13. The probe 12, shown in detail in FIG. 4, is generally a printed card circuit 14 provided with metal tips 15 coinciding with the connection pads of the integrated circuits 2. The silicon wafer 1 is positioned on a chuck 16 that is mobile in the horizontal plane and the integrated circuits 2 are tested one after the other by shifts and by upward and downward motions of the chuck 16. The entire system is driven by a test program loaded into a memory 17 that controls the shifts of the chuck 16 and determines the electrical characteristics of the test signals to be applied to the integrated circuits.
Despite its advantages, the electrical test of integrated circuits on silicon wafers is a process that proves to be long and costly. A full test sequence for an integrated circuit comprises various test steps that are independent of one another and have to be successively performed so that the integrated circuit may be considered to be xe2x80x9cgoodxe2x80x9d, namely suitable for commercial distribution. Each test step enables the checking of an electrical or logic characteristic of the integrated circuit and requires from a few milliseconds to some hundreds of milliseconds in order to be performed. In all, a full test sequence may last several seconds. This duration multiplied by the number of integrated circuits to be tested gives a total test time that is not negligible. For example, the test of a wafer of 6,000 integrated circuits, each requiring 5 seconds to be tested, takes more than eight hours if the integrated circuits are tested one after the other.
To overcome this drawback, test probes for the simultaneous test of several integrated circuits have emerged. Thus, there has been a passage from the individual test of integrated circuits to the simultaneous test of 4, then 8 and then 16 integrated circuits. The latest equipment enables the simultaneous test of up to 32 simple integrated circuits such as EEPROM memories. However, the technique of simultaneous test is not the best approach in terms of cost, for the complexity and price of the test equipment increase proportionally with the number of simultaneously tested integrated circuits.
Another method that considerably reduces test time consists in testing only a part of the integrated circuits on a silicon wafer by xe2x80x9cskipping overxe2x80x9d integrated circuits along the rows of integrated circuits. This method enables the detection of the silicon wafers that are entirely xe2x80x9cbadxe2x80x9d because of problems occurring during manufacture. However, this method does not enable the efficient detection of the defective integrated circuits distributed randomly on a silicon wafer and thus gives low yields.
Thus, the manufacturers of integrated circuits are divided between the need for fully testing all the integrated circuits to obtain a yield of 100% of xe2x80x9cgoodxe2x80x9d integrated circuits at the exit from the production line and the temptation to test only a part of the integrated circuits in order to reduce costs and electrical test time with the risk of marketing defective integrated circuits.
The present invention seeks to overcome this drawback.
More particularly, a goal of the present invention is a method that substantially reduces the test time for a set of integrated circuits and, at the same time, gives high yields.
To achieve this goal, the present invention is based on the observation that the various test steps that constitute a full test sequence for an integrated circuit do not provide the same results in statistical terms. In practice, it is constant that certain test steps enable the detection of a high percentage of defective integrated circuits present on a silicon wafer, whereas others detect only a small number of them. Thus, from a statistical viewpoint, there are essential test steps and secondary test steps with respect to the efficiency of the test process.
On the basis of these observations, the present invention provides for a test method comprising preliminary steps consisting of the classification of the elementary test steps into statistically essential test steps and statistically secondary test steps and defining a limited test sequence that comprises only statistically essential elementary test steps, the method including a test loop comprising: a first test step consisting in testing K integrated circuits by the application, to each integrated circuit, of a full test sequence, and a second test step consisting in testing N following integrated circuits by applying a reduced test sequence to each integrated circuit.
According to one mode of implementation, the method comprises a third test step consisting of the test of M following integrated circuits by the application, to each integrated circuit, of a full test sequence if the number of integrated circuits having failed in at least one statistically secondary test step during the first step is greater than or equal to a predetermined number Q1.
According to one mode of implementation, the second test step is deactivated by the application of a full test sequence to all the integrated circuits remaining on the silicon wafer, when the number of integrated circuits having failed in at least one statistically secondary test step during the third step is greater than or equal to a predetermined number Q2.
According to one mode of implementation, the second test step is deactivated by applying a full test sequence to all the integrated circuits remaining on the silicon wafer when the number of integrated circuits having failed in at least one statistically secondary test step during the first step is greater than or equal to a predetermined number Q3.
When several silicon wafers comprising the same type of integrated circuit are tested one after the other, the second test step may be deactivated for all the integrated circuits of a silicon wafer when the number of previously tested silicon wafers for which a deactivation of the second test step has taken place is greater than a predetermined number.
The present invention also relates to a system for testing integrated circuits comprising a test probe and a test station programmed to carry out the method according to the invention.